The first FPGA with programmable logic cells and programmable routing was described by Freeman in U.S. Pat. No. 4,870,302, reissued as Re. Pat. No. 34,363, which is incorporated herein by reference. An FPGA includes configurable logic blocks and configurable routing, which are programmed by configuration memory cells. The configuration memory cells are typically arranged in an array and are loaded with a bit stream of configuration data. The configuration data is selected to cause the FPGA to perform a desired function.
FIG. 1A shows a conventional array of configuration memory cells (i.e., a configuration memory array) such as that used by Xilinx, Inc., assignee of the present invention. The configuration memory array of FIG. 1A is a 16-bit by 16-bit array, which includes 256 configuration memory cells. In general, each of the configuration memory cells is identified by a reference character Mx,y, where x and y correspond to the row and column of the configuration memory cell. A typical array of configuration memory cells in a commercial device has on the order of 20,000 to one million memory cells. Therefore, the array of FIG. 1A is much smaller than is typically used in a commercial embodiment, but nevertheless shows the structure of prior art configuration memories.
To load data into the configuration memory array shown in FIG. 1A, the bit stream of configuration data is shifted through a data shift register DSR under control of a clocking mechanism until a frame of data (16 bits wide in this example) has been shifted into bit positions DS0 through DS15 of the data shift register DSR. This frame of data is then shifted in parallel on data lines D0 through D15 into a column of configuration memory cells addressed by address shift register ASR. The column is addressed by shifting a token high bit through the address shift register ASR from bit AS0 to bit AS15, one shift per frame. Each time a frame of configuration data is loaded through data shift register DSR, it is shifted in parallel to the column of memory cells selected by the token high bit. When the token high bit shifts out to the right, it activates a DONE circuit, which indicates that configuration is complete and causes the FPGA to become operational.
FIG. 1B is a simplified circuit diagram showing memory cell M0,0. Memory cell M0,0 includes a latch formed by inverters I1 and I2 that stores a bit value transmitted through a pass transistor T1. During configuration, when the token high bit is shifted into address shift register bit AS0 (FIG. 1A), the resulting high signal on line A0 is applied to the gate of pass transistor T1, thereby allowing the configuration bit stored in data shift register bit position DS0 to enter the latch via data line D0. The value stored in memory cell M0,0 is then applied via output line Q and/or Q-bar (QB) to control a corresponding configurable logic block or configurable routing resource.
While the configuration circuitry described above is adequate for configuring the conventional configuration memory array shown in FIG. 1A, it is inadequate for performing more advanced operations. For example, the configuration circuitry does not support partial reconfiguration (i.e., changing only some of the configuration data without addressing all of the configuration memory cells) because there is no mechanism for addressing individual frames.